1. Technical Field
This disclosure relates to integrated circuit (IC) design, and more particularly to functional equivalence verification of integrated circuit logic designs.
2. Description of the Related Art
In IC design, when a reference design must be modified, in some cases it is desirable and indeed necessary to prove that the modified version of the reference IC design is functionally equivalent through a formal approach. This is sometimes necessary to ensure that no bugs have been created when the design was altered.
There are many approaches to formally proving that modifications to the design are functionally equivalent. These formal proofs can be time-consuming and resource intensive. Accordingly, it may be desirable to allow a designer to have high confidence that the modified design is functionally equivalent to the reference design in a short amount of time, even if the process does not formally prove that the change is equivalent. This may allow for more progress to be made while still catching many faults.
A conventional approach involves running the original reference design alongside the modified design in a lockstep simulation. This involves stimulating the designs identically, and then checking a set of outputs at each cycle to ensure that both designs behave identically for the stimulus that has been applied.
However, although this approach may be effective at finding faults, it has several drawbacks. More particularly, at build time two copies of the model must be built, which takes more time and more processing memory. In addition, at run time simulating two designs simultaneously (i.e., co-simulation) takes much more time and more memory. Furthermore, the simulation model must be maintained as the project progresses.